//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 unused
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module sysUseCondEqNEqCross1(CLK,
			     RST_N);
  input  CLK;
  input  RST_N;

  // register a
  reg [15 : 0] a;
  wire [15 : 0] a$D_IN;
  wire a$EN;

  // register dest
  reg [31 : 0] dest;
  wire [31 : 0] dest$D_IN;
  wire dest$EN;

  // register source1
  reg [31 : 0] source1;
  wire [31 : 0] source1$D_IN;
  wire source1$EN;

  // register source2
  reg [31 : 0] source2;
  wire [31 : 0] source2$D_IN;
  wire source2$EN;

  // remaining internal signals
  wire [31 : 0] shared__h204;

  // register a
  assign a$D_IN = 16'h0 ;
  assign a$EN = 1'b0 ;

  // register dest
  assign dest$D_IN = (a == 16'd1) ? shared__h204 : 32'd2 ;
  assign dest$EN = 1'd1 ;

  // register source1
  assign source1$D_IN = 32'd0 ;
  assign source1$EN = 1'd1 ;

  // register source2
  assign source2$D_IN = 32'd0 ;
  assign source2$EN = 1'd1 ;

  // remaining internal signals
  assign shared__h204 = (a == 16'd2) ? source2 : source1 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (a$EN) a <= `BSV_ASSIGNMENT_DELAY a$D_IN;
    if (dest$EN) dest <= `BSV_ASSIGNMENT_DELAY dest$D_IN;
    if (source1$EN) source1 <= `BSV_ASSIGNMENT_DELAY source1$D_IN;
    if (source2$EN) source2 <= `BSV_ASSIGNMENT_DELAY source2$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    a = 16'hAAAA;
    dest = 32'hAAAAAAAA;
    source1 = 32'hAAAAAAAA;
    source2 = 32'hAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    $display(shared__h204);
    if (a == 16'd1)
      $display("Error: \"UseCondEqNEqCross1.bsv\", line 23, column 9: (R0002)\n  Conflict-free rules RL_test2 and RL_test1 called conflicting methods read\n  and write of module instance source1.\n");
  end
  // synopsys translate_on
endmodule  // sysUseCondEqNEqCross1