//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 unused
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module sysUseCondFalseFalse(CLK,
			    RST_N);
  input  CLK;
  input  RST_N;

  // register a
  reg a;
  wire a$D_IN, a$EN;

  // register b
  reg b;
  wire b$D_IN, b$EN;

  // register c
  reg c;
  wire c$D_IN, c$EN;

  // register dest1
  reg [31 : 0] dest1;
  wire [31 : 0] dest1$D_IN;
  wire dest1$EN;

  // register dest2
  reg [31 : 0] dest2;
  wire [31 : 0] dest2$D_IN;
  wire dest2$EN;

  // register source
  reg [31 : 0] source;
  wire [31 : 0] source$D_IN;
  wire source$EN;

  // register a
  assign a$D_IN = 1'b0 ;
  assign a$EN = 1'b0 ;

  // register b
  assign b$D_IN = 1'b0 ;
  assign b$EN = 1'b0 ;

  // register c
  assign c$D_IN = 1'b0 ;
  assign c$EN = 1'b0 ;

  // register dest1
  assign dest1$D_IN = a ? 32'd2 : (b ? 32'd0 : source) ;
  assign dest1$EN = 1'd1 ;

  // register dest2
  assign dest2$D_IN = a ? 32'd1 : (c ? 32'd0 : source) ;
  assign dest2$EN = 1'd1 ;

  // register source
  assign source$D_IN = 32'd0 ;
  assign source$EN = 1'd1 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (a$EN) a <= `BSV_ASSIGNMENT_DELAY a$D_IN;
    if (b$EN) b <= `BSV_ASSIGNMENT_DELAY b$D_IN;
    if (c$EN) c <= `BSV_ASSIGNMENT_DELAY c$D_IN;
    if (dest1$EN) dest1 <= `BSV_ASSIGNMENT_DELAY dest1$D_IN;
    if (dest2$EN) dest2 <= `BSV_ASSIGNMENT_DELAY dest2$D_IN;
    if (source$EN) source <= `BSV_ASSIGNMENT_DELAY source$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    a = 1'h0;
    b = 1'h0;
    c = 1'h0;
    dest1 = 32'hAAAAAAAA;
    dest2 = 32'hAAAAAAAA;
    source = 32'hAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if ((!c || !b) && !a)
      $display("Error: \"UseCondFalseFalse.bsv\", line 18, column 9: (R0002)\n  Conflict-free rules RL_test2 and RL_test1 called conflicting methods read\n  and write of module instance source.\n");
  end
  // synopsys translate_on
endmodule  // sysUseCondFalseFalse