//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module sysImportForeignModule(CLK,
			      RST_N);
  input  CLK;
  input  RST_N;

  // ports of submodule the_x
  wire the_x$D_IN, the_x$EN, the_x$Q_OUT;

  // submodule the_x
  MyRegN #(.width(32'd1), .init(1'd0)) the_x(.RST(RST_N),
					     .CLK(CLK),
					     .D_IN(the_x$D_IN),
					     .EN(the_x$EN),
					     .Q_OUT(the_x$Q_OUT));

  // submodule the_x
  assign the_x$D_IN = !the_x$Q_OUT ;
  assign the_x$EN = 1'd1 ;
endmodule  // sysImportForeignModule