# -----
# Test that the derived Bits instance for Either optimizes properly.

compile_verilog_pass LeftBig.bs "" "-opt-undetermined-vals"
compare_verilog mkLeftBigReg.v

compile_verilog_pass RightBig.bs "" "-opt-undetermined-vals"
compare_verilog mkRightBigReg.v

# -----

compile_verilog_pass Maybe.bs "" "-opt-undetermined-vals"
compare_verilog mkMaybeReg.v

# -----

# Reg   = Testing that pack . unpack optimizes to the identity using registers.
# Maybe = Testing that pack . unpack optimization works for Maybes.
# Test  = Optimizing tag tests without injecting chains of != comparisons.

proc do_tests { name } {
    compile_verilog_pass ${name}.bs "" "-opt-undetermined-vals"
    compare_verilog mk${name}Reg.v
    compare_verilog mkMaybe${name}Reg.v
    compare_verilog mk${name}Test.v
}

do_tests Orig
do_tests Alt1
do_tests Alt1a
do_tests Alt2
do_tests Alt3
do_tests Alt4
do_tests Alt5
do_tests Alt6
do_tests C0
do_tests C1

# -----

# Test that pack . unpack optimizes away for enums (including non-contiguous)
compile_verilog_pass Enums.bsv

compare_verilog mkEnumType1Reg.v
compare_verilog mkEnumType2Reg.v
compare_verilog mkEnumType3Reg.v

compare_verilog mkEnumType1Test.v
compare_verilog mkEnumType2Test.v
compare_verilog mkEnumType3Test.v

# -----

# This module has one input: a union type, whose constructors take two
# arguments.  This input is decoded into separate output ports for each
# of the argument values along with a valid bit indicating when that
# union tag is present (and the associated values are valid).
# The generated expressions for the value ports should reduce to just wires.

compile_verilog_pass Decoder.bs "" "-opt-undetermined-vals -unspecified-to x"

# If mkDecoder.v does not simplify correctly, conditionals and/or Xs
# may appear in the generated output.
string_does_not_occur mkDecoder.v "xxxx"
string_does_not_occur mkDecoder.v "unspecified value"
string_does_not_occur mkDecoder.v "\?"
string_does_not_occur mkDecoder.v "case"