//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// isA                            O     1
// RDY_isA                        O     1 const
// isB                            O     1
// RDY_isB                        O     1 const
// isC                            O     1
// RDY_isC                        O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 unused
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkAlt1aTest(CLK,
		   RST_N,

		   isA,
		   RDY_isA,

		   isB,
		   RDY_isB,

		   isC,
		   RDY_isC);
  input  CLK;
  input  RST_N;

  // value method isA
  output isA;
  output RDY_isA;

  // value method isB
  output isB;
  output RDY_isB;

  // value method isC
  output isC;
  output RDY_isC;

  // signals for module outputs
  wire RDY_isA, RDY_isB, RDY_isC, isA, isB, isC;

  // register r
  reg [2 : 0] r;
  wire [2 : 0] r$D_IN;
  wire r$EN;

  // value method isA
  assign isA = r == 3'd0 || r == 3'd1 ;
  assign RDY_isA = 1'd1 ;

  // value method isB
  assign isB = r == 3'd2 || r == 3'd3 ;
  assign RDY_isB = 1'd1 ;

  // value method isC
  assign isC = r == 3'd4 || r == 3'd5 ;
  assign RDY_isC = 1'd1 ;

  // register r
  assign r$D_IN = 3'h0 ;
  assign r$EN = 1'b0 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (r$EN) r <= `BSV_ASSIGNMENT_DELAY r$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    r = 3'h2;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkAlt1aTest