//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// isA                            O     1
// RDY_isA                        O     1 const
// isB                            O     1
// RDY_isB                        O     1 const
// isC                            O     1
// RDY_isC                        O     1 const
// isD                            O     1
// RDY_isD                        O     1 const
// isE                            O     1
// RDY_isE                        O     1 const
// isF                            O     1
// RDY_isF                        O     1 const
// isG                            O     1
// RDY_isG                        O     1 const
// isH                            O     1
// RDY_isH                        O     1 const
// isI                            O     1
// RDY_isI                        O     1 const
// isJ                            O     1
// RDY_isJ                        O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 unused
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkC0Test(CLK,
		RST_N,

		isA,
		RDY_isA,

		isB,
		RDY_isB,

		isC,
		RDY_isC,

		isD,
		RDY_isD,

		isE,
		RDY_isE,

		isF,
		RDY_isF,

		isG,
		RDY_isG,

		isH,
		RDY_isH,

		isI,
		RDY_isI,

		isJ,
		RDY_isJ);
  input  CLK;
  input  RST_N;

  // value method isA
  output isA;
  output RDY_isA;

  // value method isB
  output isB;
  output RDY_isB;

  // value method isC
  output isC;
  output RDY_isC;

  // value method isD
  output isD;
  output RDY_isD;

  // value method isE
  output isE;
  output RDY_isE;

  // value method isF
  output isF;
  output RDY_isF;

  // value method isG
  output isG;
  output RDY_isG;

  // value method isH
  output isH;
  output RDY_isH;

  // value method isI
  output isI;
  output RDY_isI;

  // value method isJ
  output isJ;
  output RDY_isJ;

  // signals for module outputs
  wire RDY_isA,
       RDY_isB,
       RDY_isC,
       RDY_isD,
       RDY_isE,
       RDY_isF,
       RDY_isG,
       RDY_isH,
       RDY_isI,
       RDY_isJ,
       isA,
       isB,
       isC,
       isD,
       isE,
       isF,
       isG,
       isH,
       isI,
       isJ;

  // register r
  reg [6 : 0] r;
  wire [6 : 0] r$D_IN;
  wire r$EN;

  // value method isA
  assign isA = r[6:5] == 2'd1 && r[2:1] == 2'd0 ;
  assign RDY_isA = 1'd1 ;

  // value method isB
  assign isB = r[6:5] == 2'd1 && r[2:1] == 2'd1 ;
  assign RDY_isB = 1'd1 ;

  // value method isC
  assign isC = r[6:5] == 2'd1 && r[2:1] == 2'd2 ;
  assign RDY_isC = 1'd1 ;

  // value method isD
  assign isD = r[6:5] == 2'd1 && r[2:1] == 2'd3 ;
  assign RDY_isD = 1'd1 ;

  // value method isE
  assign isE = r[6:5] == 2'd0 ;
  assign RDY_isE = 1'd1 ;

  // value method isF
  assign isF = r[6:5] == 2'd1 ;
  assign RDY_isF = 1'd1 ;

  // value method isG
  assign isG = r[6:5] == 2'd2 ;
  assign RDY_isG = 1'd1 ;

  // value method isH
  assign isH = r[6:5] == 2'd2 && r[4:3] == 2'd0 ;
  assign RDY_isH = 1'd1 ;

  // value method isI
  assign isI = r[6:5] == 2'd2 && r[4:3] == 2'd1 ;
  assign RDY_isI = 1'd1 ;

  // value method isJ
  assign isJ = r[6:5] == 2'd2 && r[4:3] == 2'd2 ;
  assign RDY_isJ = 1'd1 ;

  // register r
  assign r$D_IN = 7'h0 ;
  assign r$EN = 1'b0 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (r$EN) r <= `BSV_ASSIGNMENT_DELAY r$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    r = 7'h2A;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkC0Test