//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// isH                            O     1
// RDY_isH                        O     1 const
// isI                            O     1
// RDY_isI                        O     1 const
// isJ                            O     1
// RDY_isJ                        O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 unused
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkC1Test(CLK,
		RST_N,

		isH,
		RDY_isH,

		isI,
		RDY_isI,

		isJ,
		RDY_isJ);
  input  CLK;
  input  RST_N;

  // value method isH
  output isH;
  output RDY_isH;

  // value method isI
  output isI;
  output RDY_isI;

  // value method isJ
  output isJ;
  output RDY_isJ;

  // signals for module outputs
  wire RDY_isH, RDY_isI, RDY_isJ, isH, isI, isJ;

  // register r
  reg [4 : 0] r;
  wire [4 : 0] r$D_IN;
  wire r$EN;

  // value method isH
  assign isH = r[4:3] == 2'd0 ;
  assign RDY_isH = 1'd1 ;

  // value method isI
  assign isI = r[4:3] == 2'd1 ;
  assign RDY_isI = 1'd1 ;

  // value method isJ
  assign isJ = r[4:3] == 2'd2 ;
  assign RDY_isJ = 1'd1 ;

  // register r
  assign r$D_IN = 5'h0 ;
  assign r$EN = 1'b0 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (r$EN) r <= `BSV_ASSIGNMENT_DELAY r$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    r = 5'h0A;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkC1Test