//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// RDY__write                     O     1 const
// _read                          O     3 reg
// RDY__read                      O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 unused
// _write_1                       I     3 reg
// EN__write                      I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkOrigReg(CLK,
		 RST_N,

		 _write_1,
		 EN__write,
		 RDY__write,

		 _read,
		 RDY__read);
  input  CLK;
  input  RST_N;

  // action method _write
  input  [2 : 0] _write_1;
  input  EN__write;
  output RDY__write;

  // value method _read
  output [2 : 0] _read;
  output RDY__read;

  // signals for module outputs
  wire [2 : 0] _read;
  wire RDY__read, RDY__write;

  // register r
  reg [2 : 0] r;
  wire [2 : 0] r$D_IN;
  wire r$EN;

  // action method _write
  assign RDY__write = 1'd1 ;

  // value method _read
  assign _read = r ;
  assign RDY__read = 1'd1 ;

  // register r
  assign r$D_IN = _write_1 ;
  assign r$EN = EN__write ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (r$EN) r <= `BSV_ASSIGNMENT_DELAY r$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    r = 3'h2;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkOrigReg