//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 unused
// RST_N                          I     1 unused
// a                             IO     5 inout
// b                             IO     5 inout
// c                             IO     5 inout
// d                             IO     5 inout
// e                             IO     5 inout
// f                             IO     5 inout
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkFourInoutBuses(CLK,
			RST_N,
			.a(a),
			.b(a),
			.c(o$FOO),
			.d(d),
			.e(d),
			.f(d));
  input  CLK;
  input  RST_N;
  inout  [4 : 0] a;
  inout  [4 : 0] o$FOO;
  inout  [4 : 0] d;

  // ports of submodule h
  wire [4 : 0] h$FOO;

  // ports of submodule o
  wire [4 : 0] o$FOO;

  // submodule g
  InoutArgStub g(.ARG(d));

  // submodule h
  InoutStubSrc1 h(.FOO(h$FOO));

  // submodule i
  InoutArgStub i(.ARG(h$FOO));

  // submodule j
  InoutStubSrc2 j(.BAR(h$FOO));

  // submodule k
  InoutStubSrc2 k(.BAR(a));

  // submodule l
  InoutStubSrc2 l(.BAR(a));

  // submodule m
  InoutArgStub m(.ARG(a));

  // submodule n
  InoutStubSrc1 n(.FOO(o$FOO));

  // submodule o
  InoutStubSrc1 o(.FOO(o$FOO));

  // submodule p
  InoutStubSrc1 p(.FOO(o$FOO));

  // submodule q
  InoutArgStub q(.ARG(o$FOO));
endmodule  // mkFourInoutBuses