//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 unused
// RST_N                          I     1 unused
// a                             IO     5 inout
// b                             IO     5 inout
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkInoutBus2(CLK,
		   RST_N,
		   .a(a),
		   .b(a));
  input  CLK;
  input  RST_N;
  inout  [4 : 0] a;

  // submodule c
  InoutStubSrc1 c(.FOO(a));

  // submodule d
  InoutStubSrc2 d(.BAR(a));

  // submodule e
  InoutArgStub e(.ARG(a));
endmodule  // mkInoutBus2