//
// Generated by Bluespec Compiler
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 unused
// RST_N                          I     1 unused
// a                             IO     5 inout
// b                             IO     5 inout
// c                             IO     5 inout
// d                             IO     5 inout
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkTwoInoutBuses(CLK,
		       RST_N,
		       .a(a),
		       .b(a),
		       .c(a),
		       .d(h$BAR));
  input  CLK;
  input  RST_N;
  inout  [4 : 0] a;
  inout  [4 : 0] h$BAR;

  // ports of submodule h
  wire [4 : 0] h$BAR;

  // submodule e
  InoutStubSrc1 e(.FOO(a));

  // submodule f
  InoutStubSrc1 f(.FOO(a));

  // submodule g
  InoutStubSrc2 g(.BAR(h$BAR));

  // submodule h
  InoutStubSrc2 h(.BAR(h$BAR));

  // submodule i
  InoutArgStub i(.ARG(h$BAR));

  // submodule j
  InoutArgStub j(.ARG(h$BAR));

  // submodule k
  InoutArgStub k(.ARG(a));
endmodule  // mkTwoInoutBuses