checking package dependencies
compiling InoutProps_BVIArg.bsv
code generation for sysInoutProps_BVIArg starts
=== IOproperties:
Name                         I/O  size props
CLK                            I     1 clock
RST_N                          I     1 reset
io_arg                        IO    32 inout


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Verilog file created: sysInoutProps_BVIArg.v
All packages are up to date.