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| author | Rishiyur S. Nikhil <nikhil@acm.org> | 2022-09-23 18:22:53 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-24 10:22:53 +1200 |
| commit | 2ad4f82001aacf99b64bd88d5ef016cffeb85568 (patch) | |
| tree | 9217d26d1dd7a42f1b93ceec4c26063f73177f77 | |
| parent | 9764cb829ebb06bd51da43969837be648264e447 (diff) | |
| download | bsc-2ad4f82001aacf99b64bd88d5ef016cffeb85568.tar.gz bsc-2ad4f82001aacf99b64bd88d5ef016cffeb85568.tar.bz2 bsc-2ad4f82001aacf99b64bd88d5ef016cffeb85568.zip | |
Bugfixes in src/exec/bsc_build_vsim_verilator (is sh script but had b… (#499)
Verilator vsim build script: Remove bash-isms
| -rwxr-xr-x | src/exec/bsc_build_vsim_verilator | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/exec/bsc_build_vsim_verilator b/src/exec/bsc_build_vsim_verilator index f481f982..69ffe2a4 100755 --- a/src/exec/bsc_build_vsim_verilator +++ b/src/exec/bsc_build_vsim_verilator @@ -141,8 +141,8 @@ do if [ "$fbase" = "main.v" ] ; then HAS_MAIN=1 else - if [[ "$fbase" != "${BSC_TOPLEVEL_MODULE}.v" ]] ; then - BSC_VERILOG_FILES_NO_MAIN+="$f " + if [ "$fbase" != "${BSC_TOPLEVEL_MODULE}.v" ] ; then + BSC_VERILOG_FILES_NO_MAIN="$BSC_VERILOG_FILES_NO_MAIN $f" fi fi done @@ -164,11 +164,10 @@ if [ -n "$BSC_VPI_FILES" ]; then # so pass them with absolute paths for f in $BSC_VPI_FILES do - if [[ "$f" =~ ^/ ]] ; then - VPI_FILES+="$f " - else - VPI_FILES+="$PWD/$f " - fi + case $f in + /*) VPI_FILES="$VPI_FILES $f" ;; + *) VPI_FILES="$VPI_FILES $PWD/$f" ;; + esac done fi |