/testsuite/bsc.verilog/portprops/
../
InHigh.bsv
InHigh.bsv.bsc-vcomp-out.expected
InoutProps_ArgToIfc.bsv
InoutProps_ArgToIfc.bsv.bsc-vcomp-out.expected
InoutProps_BVIArg.bsv
InoutProps_BVIArg.bsv.bsc-vcomp-out.expected
InoutProps_BVIIfc.bsv
InoutProps_BVIIfc.bsv.bsc-vcomp-out.expected
InoutProps_UnusedArg.bsv
InoutProps_UnusedArg.bsv.bsc-vcomp-out.expected
InoutProps_UnusedArgBVI.bsv
InoutProps_UnusedArgBVI.bsv.bsc-vcomp-out.expected
InoutProps_UnusedIfc.bsv
InputArg_ConcatReg.bsv
InputArg_ConcatReg.bsv.bsc-vcomp-out.expected
InputArg_ExtractRegAndUnused.bsv
InputArg_ExtractRegAndUnused.bsv.bsc-vcomp-out.expected
InputArg_OneReg.bsv
InputArg_OneReg.bsv.bsc-vcomp-out.expected
InputArg_OneRegOneLogicReg.bsv
InputArg_OneRegOneLogicReg.bsv.bsc-vcomp-out.expected
InputArg_OneRegOneUnused.bsv
InputArg_OneRegOneUnused.bsv.bsc-vcomp-out.expected
InputArg_TwoReg.bsv
InputArg_TwoReg.bsv.bsc-vcomp-out.expected
InputArg_Unused.bsv
InputArg_Unused.bsv.bsc-vcomp-out.expected
InputGate_OnlyInMethodReady.bsv
InputGate_OnlyInMethodReady.bsv.bsc-vcomp-out.expected
Makefile
MethodArg_OneReg.bsv
MethodArg_OneReg.bsv.bsc-vcomp-out.expected
MethodValue_ConcatRegAndConst.bsv
MethodValue_ConcatRegAndConst.bsv.bsc-vcomp-out.expected
MethodValue_ConcatRegAndLogic.bsv
MethodValue_ConcatRegAndLogic.bsv.bsc-vcomp-out.expected
MethodValue_ConcatTwoReg.bsv
MethodValue_ConcatTwoReg.bsv.bsc-vcomp-out.expected
MethodValue_Const.bsv
MethodValue_Const.bsv.bsc-vcomp-out.expected
MethodValue_ExtractReg.bsv
MethodValue_ExtractReg.bsv.bsc-vcomp-out.expected
MethodValue_Logic.bsv
MethodValue_Logic.bsv.bsc-vcomp-out.expected
MethodValue_OneReg.bsv
MethodValue_OneReg.bsv.bsc-vcomp-out.expected
OutputClockAndReset.bsv
OutputClockAndReset.bsv.bsc-vcomp-out.expected
portprops.exp