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authorIvan Molodetskikh <yalterz@gmail.com>2024-04-22 09:14:14 +0400
committerIvan Molodetskikh <yalterz@gmail.com>2024-04-24 12:26:59 +0400
commite261b641ed62474676c90aaa4e734cdd1ecde703 (patch)
tree0f386e8c87e7a6296085d2d14b9189384fea790e /src/backend
parentdc1d2b706ce43d9fb7caac75b839a0bfc6ded029 (diff)
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Filter out the Intel CCS modifiers
Diffstat (limited to 'src/backend')
-rw-r--r--src/backend/tty.rs22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/backend/tty.rs b/src/backend/tty.rs
index 6a5b3445..f3787624 100644
--- a/src/backend/tty.rs
+++ b/src/backend/tty.rs
@@ -861,6 +861,28 @@ impl Tty {
let egl_context = renderer.as_ref().egl_context();
let render_formats = egl_context.dmabuf_render_formats();
+ // Filter out the CCS modifiers as they have increased bandwidth, causing some monitor
+ // configurations to stop working.
+ let mut render_formats = render_formats.clone();
+ render_formats.retain(|format| {
+ !matches!(
+ format.modifier,
+ Modifier::I915_y_tiled_ccs
+ // I915_FORMAT_MOD_Yf_TILED_CCS
+ | Modifier::Unrecognized(0x100000000000005)
+ | Modifier::I915_y_tiled_gen12_rc_ccs
+ | Modifier::I915_y_tiled_gen12_mc_ccs
+ // I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
+ | Modifier::Unrecognized(0x100000000000008)
+ // I915_FORMAT_MOD_4_TILED_DG2_RC_CCS
+ | Modifier::Unrecognized(0x10000000000000a)
+ // I915_FORMAT_MOD_4_TILED_DG2_MC_CCS
+ | Modifier::Unrecognized(0x10000000000000b)
+ // I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC
+ | Modifier::Unrecognized(0x10000000000000c)
+ )
+ });
+
// Create the compositor.
let mut compositor = DrmCompositor::new(
OutputModeSource::Auto(output.clone()),